Clearphone : A 0.9 V 96 μW digital hearing aid system

Author

Kim, Sunyoung ; Cho, Namjun ; Song, Seong-Jun ; Kim, Donghyun ; Kim, Kwanho ; Yoo, Hoi-Jun

Author_Institution

Dept. of EECS, Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon

fYear

2006

fDate

Nov. 29 2006-Dec. 1 2006

Firstpage

182

Lastpage

185

Abstract

A low power fully operational digital hearing aid chip, named Clearphone, is proposed and implemented. To achieve both the high energy efficiency and flexibility, it adopts the enhanced adaptive-SNR analog front-end, the dedicated DSP and the heterogeneous Sigma-Delta DAC. Implemented in a 0.18 mum standard CMOS process with a 0.9 V supply voltage, the power consumption of the overall system is only 96 muW. To achieve high flexibility, the combined gain control (CGC) preamplifier and dedicated DSP are presented. The peak SNR of the system is 79 dB and the active area is 2.8 mm times 1.1 mm.

Keywords

CMOS digital integrated circuits; biomedical electronics; hearing aids; low-power electronics; CMOS process; Clearphone; DSP; adaptive-SNR analog front-end; combined gain control; digital hearing aid system; heterogeneous Sigma-Delta DAC; power 96 muW; power consumption; voltage 0.9 V; Auditory system; CMOS process; Delta-sigma modulation; Digital signal processing chips; Energy consumption; Energy efficiency; Gain control; Power supplies; Preamplifiers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Biomedical Circuits and Systems Conference, 2006. BioCAS 2006. IEEE

Conference_Location

London

Print_ISBN

978-1-4244-0436-0

Electronic_ISBN

978-1-4244-0437-7

Type

conf

DOI

10.1109/BIOCAS.2006.4600338

Filename

4600338