Performance and area estimation based on VHDL descriptions and functional unit database

A new performance and area estimation approach is developed and presented in this paper. The method adopts a bottom-up strategy, where smaller constructs in a behavioral description are analyzed first, and larger constructs will be analyzed based on the results of smaller ones. The algorithms are developed to be applied directly, on VHDL behavioral descriptions. A functional unit database is built to supply the performance and area information on the components at the register-transfer level. This approach makes system level partitioning more practical by providing efficient and useful estimation