DocumentCode :
2592449
Title :
Area and throughput trade-offs in the design of pipelined discrete wavelet transform architectures
Author :
Silva, Sandro V. ; Bampi, Sergio
Author_Institution :
Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
fYear :
2005
fDate :
7-11 March 2005
Firstpage :
32
Abstract :
The JPEG2000 standard defines the discrete wavelet transform (DWT) as a linear space-to frequency transform of the image domain in an irreversible compression. This irreversible discrete wavelet transform is implemented by an FIR filter using 9/7 Daubechies coefficients or a lifting scheme of factorized coefficients from 9/7 Daubechies coefficients. The paper investigates the tradeoffs between area, power and data throughput (or operating frequency) of several implementations of the discrete wavelet transform using the lifting scheme in various pipeline designs. The paper shows the results of five different architectures synthesized and simulated in FPGAs. It concludes that the descriptions with pipelined operators provide the best area-power-operating frequency trade-off over non-pipelined operator descriptions. Those descriptions require around 40% more hardware to increase the maximum operating frequency up to 100% and reduce power consumption to less than 50%. Starting from behavioral HDL descriptions provides the best area-power-operating frequency trade-off, improving hardware cost and maximum operating frequency by around 30% in comparison to structural descriptions for the same power requirement.
Keywords :
FIR filters; data compression; discrete wavelet transforms; field programmable gate arrays; image coding; integrated circuit design; logic design; pipeline processing; power consumption; Daubechies coefficients; FIR filter; FPGA; JPEG2000 standard; area-power-operating frequency trade-off; area-throughput trade-off; behavioral HDL descriptions; image domain; irreversible DWT; irreversible compression; lifting scheme; linear space-to frequency transform; pipelined discrete wavelet transform architectures; power consumption; Discrete wavelet transforms; Field programmable gate arrays; Finite impulse response filter; Frequency; Hardware; Image coding; Pipelines; Throughput; Transform coding; Wavelet domain;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2288-2
Type :
conf
DOI :
10.1109/DATE.2005.66
Filename :
1395789
Link To Document :
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