• DocumentCode
    2593145
  • Title

    Design and performance evaluation of an expendable modular directory scheme for maintaining cache coherency in multiprocessor systems

  • Author

    Ososanya, Esther T. ; Matthews, Donald, Jr.

  • Author_Institution
    Dept. of Electr. Eng., Tennessee Technol. Univ., Cookeville, TN, USA
  • fYear
    1995
  • fDate
    12-14 Mar 1995
  • Firstpage
    109
  • Lastpage
    113
  • Abstract
    In multiprocessor systems with private caches, inconsistencies between blocks contained within separate catches can occur. A scheme must be devised to eliminate data inconsistencies and maintain coherency within the caches. One category of schemes for cache coherency involves using directories as an information system for the caches. In most cases the caches rely on signals from the directory as to when it can complete its operation. This paper presents a hardware based directory-arbitrator approach to the cache coherence problem. The arbitrator design is expandable and will allow parallel configuration of the directory chips to increase the number of caches that can be supported
  • Keywords
    cache storage; data integrity; information systems; multiprocessing systems; software performance evaluation; arbitrator design; block inconsistencies; cache coherence problem; cache coherency; coherency; data inconsistencies; directory chips; directory-arbitrator approach; expendable modular directory scheme; information system; multiprocessor systems; parallel configuration; performance evaluation; private cache; signals; Cache memory; Multiprocessing systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System Theory, 1995., Proceedings of the Twenty-Seventh Southeastern Symposium on
  • Conference_Location
    Starkville, MS
  • ISSN
    0094-2898
  • Print_ISBN
    0-8186-6985-3
  • Type

    conf

  • DOI
    10.1109/SSST.1995.390608
  • Filename
    390608