DocumentCode
2593169
Title
Fault modeling andsimulation based on VHDL
Author
Entrena, Luis ; Lopez, J. ; Olenz, S.
Author_Institution
TGI, S.A.
fYear
1994
fDate
30 Jun-1 Jul 1994
Keywords
Circuit faults; Circuit synthesis; Circuit testing; Design methodology; Discrete event simulation; Fabrication; Hardware design languages; Logic testing; Standards development; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop, 1994. ATW '94. The Third Annual Atlantic
Type
conf
DOI
10.1109/ATW.1994.747831
Filename
747831
Link To Document