Title :
Fault modeling andsimulation based on VHDL
Author :
Entrena, Luis ; Lopez, J. ; Olenz, S.
Author_Institution :
TGI, S.A.
fDate :
30 Jun-1 Jul 1994
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Design methodology; Discrete event simulation; Fabrication; Hardware design languages; Logic testing; Standards development; System testing;
Conference_Titel :
Test Workshop, 1994. ATW '94. The Third Annual Atlantic
DOI :
10.1109/ATW.1994.747831
