A 97mW 110MS/s 12b pipeline ADC implemented in 0.18 μm digital CMOS

Author

Andersen, Terje N. ; Briskemyr, Atle ; Telstø, Frode ; Bjørnsen, Johnny ; Bonnerud, Thomas E. ; Hernes, Bjørnar ; Moldsvor, Øystein

Author_Institution

Nordic Semicond., Trondheim, Norway

fYear

2005

fDate

7-11 March 2005

Firstpage

219

Abstract

A 12 bit pipeline ADC fabricated in a 0.18 μm pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10 MHz input signal with 2V_P-P signal swing is applied. The occupied silicon area is 0.86 mm² and the power consumption equals 97 mW. A switched capacitor bias current circuit scales the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; pipeline processing; power consumption; switched capacitor networks; 0.18 micron; 1.8 V; 10 MHz; 12 bit; 97 mW; bias current circuit; conversion rate; digital CMOS; pipeline ADC; scaleable power consumption; switched capacitor; CMOS technology; Energy consumption; Error correction; Pipelines; Power dissipation; Silicon; Switched capacitor circuits; Switching circuits; Ultrasonic imaging; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2005. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2288-2

Type

conf

DOI

10.1109/DATE.2005.3

Filename

1395824