Title :
Testing logic cores using a BIST P1500 compliant approach: a case of study
Author :
Bernardi, P. ; Masera, G. ; Quaglio, F. ; Reorda, M. Sonza
Author_Institution :
Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
Abstract :
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in system-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures of the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.
Keywords :
built-in self test; industrial property; logic testing; standards; system-on-chip; BIST P1500; P1500 standard; SoC; area overhead; at-speed test; core IP; diagnostic capabilities; fault coverage; logic core testing; performance slowdown; reduced test time; simple test interface; system-on-a-chip; Automatic logic units; Automatic testing; Built-in self-test; Circuit testing; Computer aided software engineering; Costs; Logic devices; Logic testing; Software testing; System testing;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.305