A space vector PWM modulation scheme for back-to-back three-level diode-clamped converters

This paper proposes a modulation strategy for back-to-back NPC converters. This technique ensures that the low-frequency voltage oscillation in the dc-link capacitors is kept within established limits while minimizing the distortion of the ac side output voltages. Generally, space vector pulse width modulation schemes (SVPWM) to implement a given output voltage vector it is selected the nearest three vectors (N3V) to reduce the output distortion voltages. However this approach can lead to imbalances and oscillations in the dc-link capacitors voltages. To reduce this voltage oscillations the NS3V diagram can be used, although this technique penalize the THD of the converter output voltages. This work proposes the utilization of limits to the voltage imbalances as criterion to combine the N3V and the NS3V for the back-to-back NPC converter configuration. Thereby, it is established a compromise between the capacitor voltage oscillations and the output voltage distortion. This provide a degree of freedom to operate with a reduced THD in the voltages at the grid side while minimizing the imbalance in the dc-link voltages. Simulation results are given to demonstrate the good performance of the proposed technique.