Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits

Author

Desai, Kunal ; Krishna, Vijay

Author_Institution

Rambus India Design Center, India

fYear

2011

fDate

2-7 Jan. 2011

Firstpage

41

Lastpage

46

Abstract

For optimal operation, the Clock and Data Recovery (CDR) circuit requires perfect quadrature between In-phase and Quadrature phase clocks. These clocks are used to sample the Data and the Edge information so as to enable the CDR to align the Receiver clock to the centre of Data eye. Any error in quadrature between the two clocks results in higher CDR jitter. Quadrature error mainly comes from the clock-path mismatch and also from mismatch between the In-phase and Quadrature-phase interpolators. A novel Quadrature Error Compensation (Calibration) mechanism to overcome the quadrature error is implemented and discussed in this paper. An improvement of 30% in the CDR jitter was obtained with the proposed mechanism for a 5 Gbps (PCIe Gen2) link implemented in a 45nm process.

Keywords

calibration; clock and data recovery circuits; error compensation; timing jitter; CDR circuit; PCIe Gen2 link; calibration; clock path mismatch; data recovery circuits; edge information; high speed clock; jitter reduction; quadrature error compensation; quadrature phase clocks; quadrature-phase interpolators; receiver clock; size 45 nm; Calibration; Clocks; Integrated circuit modeling; Jitter; Phase locked loops; Quantum cascade lasers; Table lookup; CDR jitter; Clock and data recovery (CDR); Phase Interpolator Calibration; Quadrature Error Compensation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design (VLSI Design), 2011 24th International Conference on

Conference_Location

Chennai

ISSN

1063-9667

Print_ISBN

978-1-61284-327-8

Electronic_ISBN

1063-9667

Type

conf

DOI

10.1109/VLSID.2011.30

Filename

5718775