Title :
A 1.8GHz Digital PLL in 65nm CMOS
Author :
Chattopadhyay, Biman ; Kamath, Anant S. ; Nayak, Gopalkrishna
Author_Institution :
Analog Interfaces & Sub-Syst., Texas Instrum. India Pvt. Ltd., Bangalore, India
Abstract :
A 1.8GHz high-accuracy, ring-oscillator based Digital Phase Lock Loop (DPLL), suitable for Serializer-Deserializer (SERDES) applications like HDMI, eSATA and USB2.0 is presented here. Sigma-Delta (ΣΔ) dithering followed by passive filtering, along with Temperature Compensation is used to ensure frequency accuracy and low accumulated jitter, over a large temperature range. A re-circulating delay line based Time to Digital Converter (T2D) is used to handle large phase differences between the reference and feedback clocks. The DPLL is built in 65nm technology, and provides up to 1.8GHz output, with a phase noise of -87dBc/Hz at 1 MHz offset, and a frequency accuracy of +/-100ppm. It supports input frequencies in the range 0.7MHz to 50MHz, occupies a core area of 0.11 sq mm, and does not require external components.
Keywords :
CMOS digital integrated circuits; convertors; delay lines; digital phase locked loops; jitter; oscillators; passive filters; CMOS process; DPLL; HDMI; USB2.0; digital phase lock loop; eSATA; feedback clocks; frequency 0.7 MHz to 50 MHz; frequency 1.8 GHz; low accumulated jitter; passive filtering; phase differences; recirculating delay line; ring-oscillator; serializer-deserializer application; sigma-delta dithering; size 65 nm; temperature compensation; time to digital converter; Bandwidth; Clocks; Delay; Jitter; Phase frequency detector; Phase locked loops; Phase noise;
Conference_Titel :
VLSI Design (VLSI Design), 2011 24th International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-61284-327-8
Electronic_ISBN :
1063-9667
DOI :
10.1109/VLSID.2011.32
