Systematic analysis for static and dynamic drops in power supply grids of 3-D integrated circuits

In recent emerging 3-D chip integration techniques, on-chip power supply grids are interconnected vertically by through silicon vias (TSVs). The operational currents required by each functional device in the integrated circuits (ICs) are supplied through vertical power and ground TSVs, and horizontal power grids. Accurate estimation of power supply noise (i.e., static and dynamic drops) in a 3-D power distribution network is crucial for a robust power supply design. Fast switching speed of the devices complicated the accurate analysis of the worst case power supply noise. In this paper, we present a systematic approach to analyse the static and dynamic drops for the power supply grids in 3-D ICs. The approach is further extended to study the planning of decoupling capacitors in 3D ICs to contain power supply noise.