DocumentCode
2595862
Title
Single Event Upset Detection and Correction
Author
Singh, Jawar ; Mathew, J. ; Hosseinabady, M. ; Pradhan, D.K.
Author_Institution
Univ. of Bristol, Bristol
fYear
2007
fDate
17-20 Dec. 2007
Firstpage
13
Lastpage
18
Abstract
This paper proposes a low cost solution to detect and correct a transient faults in registers of a design. The proposed method realizes a single-event upset detection and correction (SEU-DC) technique. The detection and correction of SEU in registers of a design is difficult and requires some efficient approaches without significant area overhead and timing penalty. Furthermore, the proposed method is based on the traditional parity codes to detect and correct a single-bit error without significant increase in area overhead. We conducted experiments on the MCNC benchmark circuits which show that present approach has very low area overhead and timing penalty as compared to hardware redundancy approach.
Keywords
circuit reliability; error correction; logic circuits; parity check codes; MCNC benchmark circuits; overhead penalty; parity codes; single event upset correction; single event upset detection; timing penalty; Circuit faults; Costs; Error correction codes; Event detection; Fault detection; Hardware; Redundancy; Registers; Single event upset; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology, (ICIT 2007). 10th International Conference on
Conference_Location
Orissa
Print_ISBN
0-7695-3068-0
Type
conf
DOI
10.1109/ICIT.2007.60
Filename
4418259
Link To Document