150 μm pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects

Low-k test vehicles with four Cu layers are fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution is applied using wafer integration technology to minimize the stress from the solder bump pad to low-k ILD (interlayer dielectric). Two different interconnections were studied; i) Pb-free solder bump and ii) copper column. Ti/NiV/Cu/Au UBM is deposited on the Cu/low-k wafers and Sn-4.0Ag-0.5Cu Pb-free solder are bumped for solder interconnection. For copper column interconnection, thick PR process is developed and optimized for electro Cu plating and solder is deposited on the top of Cu post. Bump shear test is carried out to evaluate the bump bonding and analyzed the failure. In order to investigate UBM and solder joint reliability, multiple reflows were carried out. Microstructure observation and failure analysis were performed and observed with optical and electron microscopy. The paper will also present the reliability and failure analysis studies carried out in characterizing the UBM structures.