Title :
Low temperature process evaluation for 3DIC integrated thin wafer handling
Author :
Chen, Y.H. ; Tsai, W.L. ; Chang, H.H. ; Chien, C.H. ; Fu, H.C. ; Chiang, C.W. ; Lo, W.C.
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
The goal of temporary wafer bonding for 3DIC thin wafer handling is less topographic issues and high temperature resistance. The wafer thinning and process in vacuum chamber with high temperature are the key for the 3DIC thin wafer handling. In this article a quick adhesive selecting methods, and process improvement results are evaluated and discussed.
Keywords :
cryogenic electronics; three-dimensional integrated circuits; wafer bonding; 3DIC integrated thin wafer handling; high temperature resistance; low temperature process evaluation; quick adhesive selecting methods; temporary wafer bonding; vacuum chamber; wafer process; wafer thinning; Bonding; Power demand; Resistance; Silicon; Thermal stability; Through-silicon vias;
Conference_Titel :
Low Temperature Bonding for 3D Integration (LTB-3D), 2012 3rd IEEE International Workshop on
Conference_Location :
Tokyo
Print_ISBN :
978-1-4673-0743-7
DOI :
10.1109/LTB-3D.2012.6238095
