• DocumentCode
    2597836
  • Title

    Design considerations on solder joint reliability of dual row quad flat no-lead packages

  • Author

    Ying, Ming ; Chow, Seng Guan ; Punzalan, Jefiey D. ; Emigh, Roger ; Ramakrishna, Kambhampati

  • Author_Institution
    STATS ChipPAC Ltd., Singapore, Singapore
  • fYear
    2004
  • fDate
    8-10 Dec. 2004
  • Firstpage
    308
  • Lastpage
    312
  • Abstract
    The present studies are to determine the largest possible package body size and die size for dual row quad flat no-lead package feasibility designs by taking the warpage and solder joint board level reliability into consideration. The impacts of solder materials and lead finishing are also investigated. A three-dimensional finite element analysis is conducted to predict the solder joint creep behavior under a board level temperature cycling condition as defined in JEDEC specification. In order to model the solder joint structure in more detail without significantly increasing computational time, the global/local model approach is utilized. Since the first failure cycle for solder joint is of most interested during package development, the Coffin-Manson relationship between the first failure cycle and the incremental sectional-area averaged equivalent creep strain per temperature cycle simulated with finite element method is provided. The first failure cycle for solder joint can be then estimated with the Coffin-Manson fatigue life mode. Hence, the maximum package body size and die size can be optimized accordingly to suit application requirements.
  • Keywords
    creep fracture; electronics packaging; finite element analysis; semiconductor device reliability; solders; Bluetooth; Coffin-Manson fatigue life; JEDEC specification; analog baseband; board level temperature cycling condition; design considerations; die size; dual row quad flat no-lead packages; failure cycle; finite element analysis; global/local model approach; lead finishing; package body size; package feasibility designs; power management; solder joint board level reliability; solder joint creep behavior; solder joint reliability; solder materials; warpage consideration; wireless handset; Capacitive sensors; Computational modeling; Conducting materials; Creep; Finishing; Finite element methods; Lead; Packaging; Soldering; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th
  • Print_ISBN
    0-7803-8821-6
  • Type

    conf

  • DOI
    10.1109/EPTC.2004.1396624
  • Filename
    1396624