HIPERMA: A high performance and reconfigurable processor for SAR applications

Author

Qiao, Shushan ; Hei, Yong ; Xu, Xinfeng ; Wu, Bin ; Zhou, Yumei

Author_Institution

Chinese Acad. of Sci., Beijing

fYear

2007

fDate

5-9 Nov. 2007

Firstpage

240

Lastpage

243

Abstract

In this paper, a high performance and reconfigurable MAC Array (HIPERMA) processor is designed for Synthetic Aperture Radar (SAR) systems. HIPERMA is composed of many coarse-grained reconfigurable units and can be configured to finish the algorithms based on matrix multiplication level. The processor maintains the performance of ASIC devices and flexibility of DSP, and also has inherent advantages over FPGA in terms of delay, area and configuration time. The measurement result shows it has a peak performance up to 20,000 MMACS based on SMIC 0.18 urn six-metal CMOS process.

Keywords

CMOS integrated circuits; application specific integrated circuits; digital signal processing chips; field programmable gate arrays; matrix multiplication; radar signal processing; reconfigurable architectures; synthetic aperture radar; ASIC device; CMOS; DSP; FPGA; SAR; matrix multiplication; reconfigurable MAC array processor; size 0.18 mum; synthetic aperture radar; Application specific integrated circuits; Computer architecture; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Hardware; Reconfigurable architectures; Signal processing; Signal processing algorithms; Synthetic aperture radar;

fLanguage

English

Publisher

ieee

Conference_Titel

Synthetic Aperture Radar, 2007. APSAR 2007. 1st Asian and Pacific Conference on

Conference_Location

Huangshan

Print_ISBN

978-1-4244-1188-7

Electronic_ISBN

978-1-4244-1188-7

Type

conf

DOI

10.1109/APSAR.2007.4418599

Filename

4418599