Digital NN implementations in a FPGA for distance measurement and surface classification

A Neural Network (NN), implemented in 0.35 μm CMOS technology, was integrated in order to increase the distance range of a phase-shift laser range-finder and to achieve surface discrimination. The overall sensor was validated for well defined experimental conditions. Then, a digital updating system was developed, so that the embedded sensor achieves its task autonomously onboard the application, whatever the experimental conditions. Nevertheless, if a digital implementation was justified by the parameters storage robustness and the update easiness, it led to a high number of ADCs and DACs, and then to an increase of the overall consumption and complexity. Thereby, in order to simplify the system and to decrease the sensor onboard consumption, other ways were prospected. The most promising idea was to design digitally the NN structure. If an analog NN implementation was justified in well-defined conditions, a digital NN could be more appropriate for varying experimental conditions since it limits the number of conversions. Thus, different structures of digital neurons were designed in order to emphasize the advantages and the drawbacks of both analog and digital implementation methods regarding several criterions, such as power dissipation, signal propagation speed and resolution. This paper focuses on the instrumentation and the first tests achieved on different digital neuron structures.