Fault simulation for fault-tolerant multi-Mbit RAMs

A simulation method that generates clusters with negative binomial distributions was first described by F. Flack (see Solid-State Electron., vol.28, p.555-9, June 1985). The present author found that the results were not accurate enough for mimicking the clusters observed on actual chips. An alternative technique was developed and is described. The model presented makes three important changes. First, the method of generating faults as a function of time in the manufacturing process is applied to small areas within chips, instead of entire chips. Second, the parameter c is allowed to vary with position on chips and wafers, thus becoming a susceptibility function c(x,y). The third modification is the inclusion of a distance dependence on nearby faults. The yield models developed make it possible to project the productivity increases expected from future memory chips.