Title :
SOI design for submicron CMOS
Author :
Choi, J.Y. ; Fossum, J.G. ; Sundaresan, R.
Author_Institution :
Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA
Abstract :
Summary form only given. Device/circuit simulations, done with a previously developed SOI MOSFET model in SPICE and supported by measurements of devices fabricated in SIMOX films, are used to suggest optimal design for submicron SOI CMOS. The design optimization addresses hot-carrier-induced degradation, punchthrough, drain-induced barrier lowering (DIBL), and the effect of the parasitic bipolar transistor (BJT) in the thin-film, fully depleted, submicron SOI MOSFET
Keywords :
CMOS integrated circuits; hot carriers; insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; thin film transistors; SIMOX films; SOI MOSFET model; SPICE; design optimization; drain-induced barrier lowering; hot-carrier-induced degradation; optimal design; parasitic bipolar transistor; punchthrough; submicron SOI CMOS; thin film MOSFET; Bipolar transistors; Circuit simulation; Degradation; Design optimization; Hot carrier effects; Hot carriers; MOSFET circuits; SPICE; Semiconductor device modeling; Thin film transistors;
Conference_Titel :
SOS/SOI Technology Conference, 1989., 1989 IEEE
Conference_Location :
Stateline, NV
DOI :
10.1109/SOI.1989.69747
