Standard error in die yield projections from defect test structures

Large-area defect test structures provide valuable information about yield inhibitors that in most cases can be obtained only with a great deal more difficulty from VLSI circuits themselves. Effective use of the test structures depends on the sizes of the critical features on the test structure relative to the VLSI circuits being manufactures, and the errors made in estimating yield from test structure data. The standard prediction error (SPE) for die yield and its implications for test structure design are discussed. A binomial simulation of projected error is made that allows one to assess the contribution of the variation in yield from pure chance excluding error sources such as measurement errors. The simulated error is smaller than the SPE.