FPGA implementation of CIS speech processing strategy for Cochlear Implants

Continuous Interleaved Sampling (CIS) is one of the most famous speech processing approaches used in Cochlear Implants speech processors. In the future, to meet the need of totally implantable cochlear implants (TICI), the power consumption needs to be reduced. A CIS application specified integrated circuit (ASIC) has an obvious dissipation advantage compared with a DSP-based circuit. In order to design an ASIC, it is necessary to make a verification of its feasibility. A lot of papers have showed their verification work in software simulation. But this paper proposes a hardware-level CIS model working at 1MHz which can be implemented on a FPGA chip. A preliminary report containing resource occupation of the circuit scale is produced in the end. It gives us a better guidance for the design of a CIS ASIC in the next step.