Inverter propagation delay measurements using timing sampler circuits

Two timing sampler designs are described. The first design consists of a chain of 64 inverter pairs that allows the measurement of individual inverter-pair delay. The results for 3- mu m CMOS show that the delays are normally distributed with a standard deviation between 200 and 290 ps. The second design consists of 16 chains of four inverter pairs each that have different load capacitances. This structure allows the measurement of the capacitance/area of poly, metal 1, metal 2, n⁺ diffusion, gate layers, and the capacitance/length of n⁺ diffusion and p⁺ diffusion layers. An analysis of the measurement technique reveals that the delays are sensitive to the timing sampler input waveshape. A steep input risetime can distort the timing delays measured from inverter pairs located at the beginning of the chain.