Critical charge model for transient latch-up in VLSI CMOS circuits

Author

Reczek, W. ; Winnerl, J. ; Pribyl, W.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1989

fDate

13-14 March 1989

Firstpage

251

Lastpage

254

Abstract

Experimental results and theoretical considerations on the critical charge model for latch-up in VLSI CMOS circuits are presented. The critical charge is constant, proportional to the trigger phase pulse height, and inversely proportional to the trigger pulse width. With these results it is possible to calculate the transient latch-up susceptibility of circuits due to periodic pulses, e.g. overshoot, undershoot, and glitches.

Keywords

CMOS integrated circuits; VLSI; integrated circuit testing; transients; VLSI CMOS circuits; critical charge model; glitches; overshoot; periodic pulses; transient latch-up; trigger phase pulse height; trigger pulse width; undershoot; Circuit testing; Current measurement; Pulse circuits; Pulse measurements; Pulse width modulation inverters; Semiconductor device modeling; Space vector pulse width modulation; Substrates; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1989. ICMTS 1989. Proceedings of the 1989 International Conference on

Print_ISBN

0-87942-714-0

Type

conf

DOI

10.1109/ICMTS.1989.39318

Filename

39318

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2598497