Electrostatic discharge test structures for CMOS circuits

A module with test structures for the characterization of the electrostatic discharge (ESD) sensitivity of CMOS circuits a module with test structures is described. To evaluate the various types of protection circuits with statistical significance automatic ESD tests have to be performed directly on the wafer. The setup and measurement problems due to parasitic capacitances and inductances are discussed. The test method and measurement results for input-protection circuits with poly-Si contacts and n-wells are presented.