DocumentCode
2598607
Title
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method
Author
Tseng, Po-Chih ; Huang, Chao- Tsung ; Chen, Liang-Gee
Author_Institution
Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
1
fYear
2002
fDate
2002
Firstpage
363
Abstract
In this paper, by using line-based methods, a generic RAM-based architecture is proposed to construct the corresponding two-dimensional architectures efficiently for any given hardware architecture of one-dimensional wavelet filters, including conventional convolution-based and advanced lifting-based architectures. The categories of line buffer and the strategy to optimize the size of internal memory are also described. For multi-level two-dimensional discrete wavelet transforms, the recursive pyramid algorithm is adopted to turn our proposed architecture into another efficient architecture. According to the comparison results, the proposed architecture outperforms previous arts in the aspects of memory size, control complexity, and flexibility.
Keywords
buffer storage; circuit optimisation; convolution; discrete wavelet transforms; logic design; random-access storage; recursive functions; 1D wavelet filter hardware architecture; 2D discrete wavelet transform generic RAM-based architecture; DWT; RPA; advanced lifting-based architectures; architecture flexibility; control complexity; convolution-based architectures; internal memory size optimization; line buffer categories; line-based methods; multi-level 2D discrete transforms; recursive pyramid algorithms; Arithmetic; Chaos; Computer architecture; Costs; Digital signal processing; Discrete wavelet transforms; Filters; Hardware; Image coding; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN
0-7803-7690-0
Type
conf
DOI
10.1109/APCCAS.2002.1114971
Filename
1114971
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