Title :
Functional fault models and gate level coverage for sequential architectures
Author :
Buonanno, G. ; Fummi, F. ; Sciuto, D.
Author_Institution :
Dipartimento di Elettronica, Politecnico di Milano, Italy
Abstract :
This paper introduces and evaluates functional fault models for test pattern generation of sequential circuits at the finite state machine level. Evaluation of the proposed fault models against their gate level fault coverage on multi-level implementations is presented. The relationships between functional and gate level fault coverage are discussed
Keywords :
circuit analysis computing; fault diagnosis; finite state machines; logic testing; multivalued logic circuits; sequential circuits; finite state machine level; functional fault models; gate level fault coverage; multi-level implementations; sequential architectures; sequential circuits; test pattern generation; Automata; Automatic testing; Bridge circuits; Circuit faults; Circuit testing; Fault detection; Performance analysis; Performance evaluation; Sequential analysis; Sequential circuits;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393312
