Test bench modeling and characterization for fine pitch wafer level packaged devices

Author

Jayabalan, Jayasanker ; Mihai, Rotaru D. ; Tan, Jimmy P H ; Iyer, Mahadevan K. ; Leong, Ooi Ban ; Seng, Leong Mook

Author_Institution

Nat. Univ. of Singapore, Singapore

fYear

2004

fDate

8-10 Dec. 2004

Firstpage

502

Lastpage

505

Abstract

This work describes an interposer hardware for testing fine pitch wafer level packaged devices. It is built to handle multi-gigahertz signal propagation using 100 micron pitch GSG probes. All the components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB and trampoline mesh have been modeled. A sample chip, without bumps on the pads, has also been measured. The measurement and models demonstrate that the test socket performs at 5 GHz with an insertion loss of about 3dB.

Keywords

chip scale packaging; fine-pitch technology; integrated circuit testing; wafer bonding; 5 GHz; PCB; SMA connector; coplanar transmission line; fine pitch wafer level package devices; interconnect modeling; interposer hardware; multigigahertz signal propagation; pitch GSG probe; test bench modeling; test hardware socket; trampoline mesh; Connectors; Hardware; Packaging; Probes; Semiconductor device measurement; Semiconductor device modeling; Sockets; Testing; Transmission line measurements; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th

Print_ISBN

0-7803-8821-6

Type

conf

DOI

10.1109/EPTC.2004.1396660

Filename

1396660