Title :
Complex gate performance improvement by jog insertion into transistor gates
Author :
Hindmarsh, Ronald D.
Author_Institution :
Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
Abstract :
This paper describes how the insertion of 45 degree jogs into transistor gates leads to performance improvement of static CMOS complex gates. Therefore, CMOS complex gates were designed using a new layout style called Jogged Gate Matrix Layout (JOGM). SPICE3 simulation results exhibit an up to 44% speed improvement in comparison to traditional gate matrix layout style, due to reduced diffusion capacitances. JOGM also improves cell width by up to 31%
Keywords :
circuit layout; circuit layout CAD; logic CAD; logic gates; transistors; Jogged Gate Matrix Layout; SPICE3; jog insertion; layout style; performance improvement; static CMOS complex gates; transistor gates; CMOS logic circuits; Capacitance; Circuit optimization; Circuit simulation; Circuit synthesis; Design automation; Design optimization; Logic design; SPICE; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393318
