DocumentCode
2599076
Title
Physically realizable gate models
Author
Stephan, Paul R. ; Brayton, Robert K.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1993
fDate
3-6 Oct 1993
Firstpage
442
Lastpage
445
Abstract
Proposes an objective criterion for determining if, given a specific circuit technology, a gate model is suitable for synthesis and verification. This is based on relating the analog circuit behavior to the digital model behavior using a formal definition of implementation. We illustrate the type of design errors which occur when the criterion is not satisfied, and introduce a gate model designed to satisfy the criterion
Keywords
analogue circuits; logic design; logic gates; analog circuit behavior; circuit technology; design errors; digital model behavior; implementation; objective criterion; physically realisable gate models; synthesis; verification; Algorithm design and analysis; Analog circuits; Circuit synthesis; Contracts; Delay; Logic devices; Optical devices; Standards development; Testing; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-4230-0
Type
conf
DOI
10.1109/ICCD.1993.393337
Filename
393337
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