Test vector compression technique in system-on-chip

Some further studies on a hybrid test vector compression technique for VLSI circuits are presented in this paper. In the method proposed herein, the test vectors are first compacted in a hybrid fashion; next, these compressed test vectors are downloaded in the on-chip memory. The decompression software is also loaded in the memory along with test data. The decompression software then decodes the compressed test vectors for testing the specific circuit under test. The current scheme incorporates some new concepts for lossless compression, viz. Burrows-Wheeler transform and associative coder of Buyanovsky transformation. The compression program need not be loaded into the embedded processor, as only the decompression of test data is needed for the automatic test equipment. The developed technique requires minimal memory; besides, the on-chip embedded processor core can be reused for normal operation after testing. The validity of the methodology has been demonstrated through multiple simulation experiments on ISCAS 85 combinational as well as ISCAS 89 sequential benchmark circuits.