DocumentCode :
2599101
Title :
Compact mm-wave power combiners in 65nm CMOS-SOI
Author :
Zhao, Yi ; Long, John R. ; Spirito, Marco
Author_Institution :
ERL/DIMES, Delft Univ. of Technol., Delft, Netherlands
fYear :
2011
fDate :
17-19 Jan. 2011
Firstpage :
33
Lastpage :
36
Abstract :
Compact, slow-wave coplanar waveguide (S-CPW) power combiners are characterized in the 60GHz band. A floating electric shield promotes slow-wave propagation, while implementation in 65nm CMOS-SOI technology allows utilization of the entire interconnect metal stack to lower losses. Measured slowing factors as high as 11 lead to a reduction in size by a factor up to 4.4 for a 60GHz combiner. Measured attenuation and insertion loss of the S-CPW combiners are <;0.3dB per λ/4 and <;0.6dB/150μm length at 60GHz, respectively, with quality factors ranging from 25 to 45. The effects of ground-signal gap and shield density on characteristic impedance, attenuation, Q-factor and effective permittivity are described.
Keywords :
CMOS integrated circuits; coplanar waveguides; power combiners; silicon-on-insulator; CMOS-SOI; characteristic impedance; compact mm-wave power combiners; coplanar waveguide; floating electric shield; frequency 60 GHz; ground signal gap; insertion loss; interconnect metal stack; quality factors; shield density; size 65 nm; slow wave propagation; Coplanar waveguides; Impedance; Insertion loss; Loss measurement; Metals; Power combiners; Prototypes; CMOS-SOI; S-CPW; Slow-wave; coplanar waveguide; power amplifiers; power combiners;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11th Topical Meeting on
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4244-8060-9
Type :
conf
DOI :
10.1109/SIRF.2011.5719323
Filename :
5719323
Link To Document :
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