Chip-in-substrate package, CiSP, technology

The structure of chip-in-substrate package, CiSP, is shown. The thin chips (50mum) are bonded on the organic substrate (BT) flatly. Subsequently, the chips are covered among the build-up dielectric layer, which can be either a RCC (resin coated copper) material or an organic dielectric material (ABF) by a lamination process. Via holes on the chip´s I/O pad and substrate are drilled by laser. The interconnection between chip and substrate is created by Cu without bump. The main issue is focused on the interfaces among different materials. This shorter interconnection can match the demand for fast electrical response application. At the same time, the stresses simulation for the interfaces or each key location in a CiSP is also investigated to optimize the manufacturing processes