Logic optimization with multi-output gates

This paper is concerned with logic optimization of multi-output gates in multi-level combinational logic circuits. We address how a concurrent minimization over multiple gates can lead to further optimization as compared to conventional single-gate minimization techniques. In particular, we provide a procedure for computing a maximally-compatible set of permissible relations for multiple-output gates. We also propose a heuristic for clustering single-output gates into multi-output gates, so that increased concurrent optimization can be obtained