Emitter CMP process optimization for self-aligned SiGe:C HBT fabrication

Using Si/SiGe CMP in the emitter module of SiGe:C HBT fabrication is an innovative approach in two respects. First, it allows one to simplify the fabrication process, enabling real low-cost HBT modules. Second, it can also be applied to form a fully self-aligned HBT structure, enabling highest RF performance. In this paper, we focus on CMP process optimization. We will show that a previous disadvantage of emitter CMP, base current relevant emitter thinning that differs with changing emitter size can be overcome by using a new, improved CMP regime. In result, previous design restrictions, introduced to maintain HBT base current scalability, can widely be relaxed. We will also demonstrate the role of a careful post-CMP cleaning procedure with respect to device and circuit yield.