VLSI implementation of universal random number generator

Author

Cui, Wei ; Chen, He ; Han, Yueqiu

Author_Institution

Dept. of Electron. Eng., Beijing Inst. of Technol., China

Volume

1

fYear

2002

fDate

2002

Firstpage

465

Abstract

A universal random number generator which can generate random numbers drawn from a uniform distribution, exponential distribution, Rayleigh distribution and Gauss distribution has been implemented as a VLSI circuit. The proposed system is based on the principle of arithmetic iteration which is implemented as a pipelined architecture. This random number generator has the characteristics of high speed, low power consumption and high output precision, and it is especially suited in communication systems and radar echo simulation environments where multi-distribution random numbers are required. The simulation and measurement results verify the validity of the design.

Keywords

Gaussian distribution; VLSI; circuit simulation; exponential distribution; integrated circuit design; integrated circuit measurement; integrated circuit modelling; iterative methods; logic design; logic simulation; low-power electronics; pipeline arithmetic; random number generation; shift registers; 16 bit; CORDIC; Gauss distributions; RNG; Rayleigh distributions; VLSI universal random number generators; arithmetic iteration; communication systems; embedded parallel shift register architecture; exponential distributions; high-speed low power consumption generators; multi-distribution random numbers; pipelined architecture; radar echo simulation environments; uniform distributions; Arithmetic; Circuit simulation; Circuit synthesis; Exponential distribution; Gaussian distribution; Helium; Random number generation; Random variables; Read only memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on

Print_ISBN

0-7803-7690-0

Type

conf

DOI

10.1109/APCCAS.2002.1115009

Filename

1115009