Analysis and control of timing jitter in digital logic arising from noise voltage sources

Timing jitter is an important factor in limiting throughput in high-performance digital circuits, e.g. those using techniques such as wave pipelining. Many of the sources of timing jitter, such as physical noise, coupling noise, and delta-I noise, are best modeled with random shifts in signal voltages. A new analysis technique for translating such noise into timing jitter characteristics is presented. The circuit is linearized about its nominal behavior and the resulting time-varying system is discretized so that the mapping from voltage noise to timing jitter can be easily calculated and characterized. In addition, the use of differential circuit techniques to improve noise immunity is discussed