Title :
Multiple-page translation for TLB
Author_Institution :
IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Traditional approaches for increasing TLB hit ratios include using more TLB entries and/or bigger page sizes. These techniques are often subject to significant costs in implementations. We illustrate techniques for improving TLB efficiency with less expensive hardware. The basic idea is to allow multiple pages translated upon each invocation of translation through page table. The proposal can improve TLB hit ratios with reasonable amount of hardware while transparent to the software. Trade-offs in using multiple page translations are illustrated through simulation results
Keywords :
buffer storage; virtual storage; TLB efficiency; TLB entries; hit ratios; multiple page translations; page sizes; translation look aside buffer; Analytical models; Computational modeling; Computer architecture; Computer simulation; Hardware; Memory architecture; Numerical simulation; Performance analysis; Proposals; Software maintenance;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393355