Design of a novel high-performance pre-discharge flip-flop (PDFF)

Flip-flop is a vital component for high-performance and reliable deep-pipelined systems in digital microprocessors. In this paper, a new pre-discharge flip-flop (PDFF) is proposed. The performance advantage of PDFF comes from the fact that its critical path is reduced significantly to only three transistors in the worst case. A detailed comparison is carried out between the proposed PDFF and previous published single-ended and pure differential flip-flops. Simulation results in the 65nm CMOS technology have shown that PDFF is able to achieve at least 15% performance improvement and 24% PDP reduction when compared to the previous proposed flip-flops.