A comparative evaluation of adders based on performance and testability

Author

Jayabharathi, Rathish ; Thomas, Thomas ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1993

fDate

3-6 Oct 1993

Firstpage

314

Lastpage

317

Abstract

Testability is becoming an increasing concern in the design of present-day VLSI systems because of their higher density and complexity. This is particularly important in the case of arithmetic units, such as adders, which form the core of any processing unit. Techniques like design for testability (DFT) have been implemented, but a methodology for evaluating and selecting a suitable adder has not been developed. We present an exhaustive comparison of adders in terms of performance, area and testability, by formulating a figure of merit, the PLUS factor. The results of this comparison can be extended to evaluate the suitability of an adder for a particular set of design goals and constraints

Keywords

adders; design for testability; logic testing; PLUS factor; adders; arithmetic units; comparative evaluation; design for testability; design goals; present-day VLSI systems; processing unit; Adders; Arithmetic; Automatic test pattern generation; Circuit faults; Circuit testing; Costs; Design for testability; Integrated circuit technology; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393359

Filename

393359