Multiplying delay locked loop (MDLL) in time-to-digital conversion

Author

Jansson, Jussi-Pekka ; Mantyniemi, Antti ; Kostamovaara, J.

Author_Institution

Dept. of Electr. & Inf. Eng., Univ. of Oulu, Oulu, Finland

fYear

2009

fDate

5-7 May 2009

Firstpage

1226

Lastpage

1231

Abstract

This paper presents the use of a multiplying delay locked loop (MDLL) for delay line-based time interval measurement. The structure is introduced together with the theory behind the performance. Measurement results obtained with a MDLL-based time digitizer designed with 0.35 μm CMOS verify the operation and calculated performance of the device. This MDLL technique with modern CMOS technology makes longrange, high-resolution, linear time interval measurement possible with a small, simple one-level interpolation architecture.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; delay lines; delay lock loops; interpolation; multiplying circuits; time measurement; CMOS technology; MDLL-based time digitizer design; delay line-based time interval measurement; multiplying delay locked loop; one-level interpolation architecture; size 0.35 mum; time-to-digital conversion; CMOS technology; Clocks; Counting circuits; Delay effects; Delay lines; Interpolation; Propagation delay; Registers; Time measurement; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2009. I2MTC '09. IEEE

Conference_Location

Singapore

ISSN

1091-5281

Print_ISBN

978-1-4244-3352-0

Type

conf

DOI

10.1109/IMTC.2009.5168642

Filename

5168642