A novel clock distribution system for CMOS VLSI

A novel all-digital clock distribution system for CMOS VLSI, capable of generating small-skew, four-phase, and non-overlap clock signals when supplied with only a one-phase clock signal, is described. The frequency of the input clock signal can be decreased by 75% without a phase-locked loop (PLL) by adopting this system. The key concept of this system is to extract phase-adjusted multi-phase clock signals from a Multi-tapped Variable Delay Line (MVDL). With the use of a 28-MHz input reference clock, this system has been applied to a 0.8-μm CMOS gate array to produce four-phase 28-MHz clock signals with 12.5% duty cycle. Using the measured delay time of the components, clock skew and delay time variations between phases are estimated to be ±0.6 ns and ±0.5 ns, respectively. Both of these values can be decreased to ±0.2 ns with the adoption of an alternative circuit configuration