DocumentCode
2599545
Title
Transient analysis of board-level drop response of lead-free chip-scale packages with experimental verifications
Author
Yeh, Chang-Lin ; Lai, Yi-Shao
Author_Institution
Stress-Reliability Lab., Adv. Semicond. Eng. Inc., Kaohsiung, Taiwan
fYear
2004
fDate
8-10 Dec. 2004
Firstpage
695
Lastpage
700
Abstract
Through the support excitation scheme, transient structural responses of a board-level chip-scale package subjected to the JEDEC drop test are analyzed using the implicit three-dimensional finite element analysis. Analyzed failure modes of the lead-free solder joints are verified with experimental observations. The effect of drop orientations on the reliability of the test vehicle is also examined.
Keywords
chip scale packaging; printed circuit testing; solders; surface mount technology; transient analysis; 3D finite element analysis; JEDEC drop test; board-level drop response; drop orientations; experimental verifications; lead-free chip-scale packages; lead-free solder joints; support excitation scheme; transient analysis; transient structural responses; Chip scale packaging; Circuit testing; Electronic equipment testing; Electronics packaging; Environmentally friendly manufacturing techniques; Lead; Semiconductor device packaging; Soldering; Transient analysis; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th
Print_ISBN
0-7803-8821-6
Type
conf
DOI
10.1109/EPTC.2004.1396697
Filename
1396697
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