Design methodology for GMICRO/500 TRON microprocessor

Describes the design methodology used for the architecture of the GMICRO/500 TRON CISC superscalar microprocessor. Its minimum performance goal is 50 MHz, 100 VAX-MIPS at 5 V. This severe goal and the CISC superscalar architecture make the design time long and require a lot of manpower and computer resources. The C language and Unix environment are used to reduce the cost of the logic simulation. Synopsis and GDT are used to accelerate the logic design and the cell/macro design. A supercomputer is used to shorten the gate-level simulation time. The total design manpower is under 603 man-months