The PowerPC 601 design methodology

To produce a marketable PowerPC microprocessor on a short development schedule, an appropriate balance was needed between a fully customized methodology and a standard cell approach. We compiled a single model of each logic partition separately for logic synthesis and for simulation. Synthesis transferred the model to a gate-level implementation and applied timing correction transforms to reach the users´ timing assertions. Floor-planning and wiring was assisted by an automated tool. Billions of cycles were run in testing the implementation against the PowerPC architecture specification. Behaviorals were written and built into the model to test the chip as it might appear in a system configuration. Careful adherence to this methodology led to a successful first pass of silicon, leaving the second iteration for additional customer requests