Specification and synthesis of a mixed-mode systems: Experiments in a VHDL environment

Discusses the specification and automated synthesis of mixed synchronous/asynchronous systems in the context of a VHDL-based design environment. We propose a flexible paradigm for describing asynchronous behavior in VHDL that supports (1) the description of behavior as a signal transition graph (STG), (2) its expression in the form of an initializable edge-triggered finite state machine, and (3) the specification of a level-sensitive asynchronous finite state machine. An important feature is that free-running signals such as clocks can be included in the asynchronous specifications. The input specification, consisting of timing diagrams and/or the behavior and interface specifications for a set of interacting processes, is mapped into an appropriate combination of hazard-free asynchronous circuits and synchronous circuits