Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

The additional operation of retrieval of the cover image at the decoder is necessary for lossless watermarking system. Taking into account this major issue, efficient implementation of reversible image watermarking needs to be addressed. This can be solved using hardware implementation. This paper focus on the digital design with pipelined architecture of reversible watermarking algorithm based on Difference Expansion (DE) which is linear and whose running time is O (n). There are three different digital architectures proposed in this paper namely dataflow architecture, optimized dataflow architecture using pipelining and the modified architecture using pipelining. All the three design is implemented on Xilinx based FPGA. To the best of our knowledge this is the first digital design and pipelined architecture proposed in the literature for reversible watermarking using difference expansion.