Channel architecture optimization for performance and routability of row-based FPGAs

Considers routability and performance-driven optimization of a segmented channel architecture for row-based field programmable gate arrays (FPGAs). The routability of a channel and the performance of the routed circuit may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. A simulated annealing-based channel segmentation optimization scheme has been developed, which enhances channel routability and performance based on the correlation between segment and net distributions. Excellent results have been obtained for a set of benchmark examples and industrial designs