A new high performance field programmable gate array family

Author

Whitney, Telle ; Schlageter, Jeff

Author_Institution

Actel Corp., Sunnyvale, CA, USA

fYear

1993

fDate

3-6 Oct 1993

Firstpage

216

Lastpage

219

Abstract

Describes a 0.8 μm FPGA CMOS family that closes the speed gap between masked programmable gate arrays and FPGAs. This architecture achieves 16-bit counter speeds of 125 MHz and 65 MHz general system performance. The Act3 architecture includes a new more flexible I/O module and two fast clocks allowing clock-to-out speeds of 10 ns. The logic module is based on the Act2 logic module, but is more uniform and thus more amenable to synthesis. This family includes parts ranging from 1500 gates to 10,000 gates. The use of a chip compiler allows rapid generation of the entire family. The key to the generation of the designs was a compact layout and schematic tile set used for the entire family, with personalization handled by the compiler

Keywords

CMOS integrated circuits; circuit layout CAD; clocks; field programmable gate arrays; logic gates; 0.8 micron; 10 ns; 125 MHz; 16-bit counter speeds; 65 MHz; Act2 logic module; Act3 architecture; FPGA CMOS family; chip compiler; compact layout; fast clocks; flexible I/O module; general system performance; high performance field programmable gate array; logic gates; masked programmable gate arrays; personalization; schematic tile set; synthesis; Clocks; Field programmable gate arrays; Logic arrays; Logic design; Logic programming; Programmable logic arrays; Routing; System performance; Tiles; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393378

Filename

393378