Determining cost-effective multiple issue processor designs

Several commercial processors, including the Motorola 88110 and the DEC Alpha, are capable of issuing multiple operations per clock cycle. Optimization of the pipeline depth and number of function units in these processors has been largely ignored due to limited semiconductor resources. Recently, advances in feature size and packaging technologies have removed these limitations. It is possible that next-generation processor designs may benefit from multiple function unit copies and optimize pipeline depths. The paper investigates the feasibility of performing synthesis at the architectural specification level. The design space is optimized for performance constrained by a hardware model of silicon area. The results of this study indicate that cost-effective high performance can be achieved with the addition of small amounts of function unit duplication. These results are also used to comment on the validity of the “benchmark suite” approach to performance evaluation and machine design