• DocumentCode
    2600341
  • Title

    Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs

  • Author

    Hu, Yuan ; Ghouse, Ahmed ; Carlson, Bradley S.

  • Author_Institution
    Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
  • fYear
    1993
  • fDate
    3-6 Oct 1993
  • Firstpage
    21
  • Lastpage
    24
  • Abstract
    An algorithm is presented to determine two lower bounds in functional pipelined data path synthesis. Given an iteration time constraint and a task initiation latency, the algorithm computes a lower bound on the number of functional units required to execute the data flow graph (DFG) of a loop body, and given a resource constraint and a task initiation latency the algorithm computes a lower bound on the number of time steps required to execute the DFG. The lower bounds not only greatly reduce the size of the solution space, but also provide a means to measure the proximity of the final solution to an optimal one. The bounds are computed in polynomial time; therefore the algorithm is very effective, especially for large DFGs. Experiments indicate that the lower bound is very tight. For all of the test cases the difference between our solution and the optimal solution is not greater than one
  • Keywords
    computational complexity; data flow graphs; high level synthesis; iterative methods; pipeline processing; program control structures; resource allocation; data path synthesis; functional pipelined data flow graphs; functional units; iteration time; iteration time constraint; loop body; lower bounds; optimal solution proximity; polynomial time; resource amount; resource constraint; solution space reduction; task initiation latency; time steps; Algorithm design and analysis; Data flow computing; Delay; Flow graphs; Integrated circuit synthesis; Optimal scheduling; Pipeline processing; Polynomials; Scheduling algorithm; Time factors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-4230-0
  • Type

    conf

  • DOI
    10.1109/ICCD.1993.393411
  • Filename
    393411